What's next in leading edge semicap - Applied Materials' platform strategy, and the battle between Lam Research and Tokyo Electron
What's next in leading edge semicap - Applied Materials' platform strategy, and the battle between Lam Research and Tokyo Electron
An overview of the semicap space in deposition, etch, coating, and more!
Introduction, a tour of current developments in advanced semicap
Semicap, or semiconductor manufacturing equipment, is a cyclical industry but one that offers attractive exposures to innovations in leading edge semis, such as the evolution of transistor architectures and advanced packaging. As transistors continue to shrink in size while featuring ever more elaborate 3D structures constructed from a variety of materials, more manufacturing process steps are needed with more advanced tools.
ASML is the key play on shrinkage, the so called Moore’s law, whereas Applied Materials, Lam Research and Tokyo Electron also offer exposure to going vertical due to their etch and deposition activities. Note also the wide variety of tools that Applied Materials provides:
After the covid semi boom of 2020-2022, the semicap industry went into a typical cyclical correction. However, semicap shares have been rallying strongly over the last half year in anticipation of a new round of strong orders coming in the near future. The drivers for these are: gate-all-around in logic, HBM and DRAM in memory, each regional geopolitical power building up its own domestic semiconductor manufacturing capacity, and naturally all of these being further boosted by structural AI demand.
This is Lam’s CFO discussing the semicap industry:
“This is a real cyclical industry. As the world came through COVID, a lot of demand frankly got pulled forward. Everybody was buying new PCs, phones, TVs, because we were all stuck at home. The industry, sometimes we mistake what's going on, some of us got a little bit confused that it was secular growth. Inventory got built with a volume assumption that was just too high and so we're still digesting that, especially in memory. NAND is still pretty soft this year, I think next year is going to be better. If you look at the investment in wafer fab equipment in NAND last year, it was down 75%, that's a shocking amount. DRAM is better, it has a product cycle and it's got high-bandwidth memory in there.”
So the industry is coming out of the trough now with DRAM leading the charge. This can easily be witnessed in ASML’s bookings which showed very strong memory orders over the last two quarters, combined with also a strong logic number in Q4:
This is Tokyo Electron’s CFO on the outlook in wafer fabrication equipment (WFE):
“Calendar 2024 WFE market is expected to be $100 billion in size. We expect that investment for leading edge DRAM will start to recover from May 2024, driven by growing demand for DDR5 and HBM among others. In calendar 2025, a full-fledged recovery in capital investment is also expected for NAND and advanced logic/ foundry with as one of the drivers AI servers, whose annual growth rate is 31%. In addition, AI will be mounted not only to servers but also to PCs and smart phones. Also, there will be demand to replace those products purchased during the COVID-19 crisis. Driven by those factors, WFE market is expected to achieve double-digit growth in 2025.
In parallel, semiconductor technology innovation will further advance. For logic, investment for 2-nanometer node will finally start. Gate-all-around-nanosheets and backside power delivery network will play a core role in the technological inflection. For DRAM, to realize DDR5 high-speed working memory, EUV lithography and High-K Metal Gate will be introduced. HBM packaging technology to realize high bandwidth, high storage and high speed memory will be evolving further.
For NAND, to realize larger storage, initiatives to deliver high stacking structures of 300 layers will start. In addition, the NAND manufacturing process is expected to adopt multi-tier stacking and bonding technology to both memory cells and peripheral circuits fabricated on different wafers. Our company offers a broad product portfolio coping with such future technology inflections and we aim to expand market share in those high value-added areas.
In the second half of fiscal 2025, the sales to NAND customers will be recovering. Inventory adjustment will continue for NAND throughout this year. For DRAM on the other hand, in particular for AI, DRAM is running short. So the active investment is expected for DRAM to start this year. In some cases, maybe the NAND line might be replaced by DRAM line in order to fill the growing demand of DRAM.”
Later this decade, as the semi industry grows to $1 trillion in size and more, semicap is expected to become a $150 to $200 billion industry, assuming a capital intensity of 15 to 20%. Capital intensities are much higher in leading edge semis though, with leading foundry TSMC spending continuously 30 to 50 percent of revenues on capex:
So two of the key drivers for semicap in the coming years will be GAA and HBM. We’ve discussed recently the current state of the HBM market, and this is what a GAA transistor looks like:
Applied Materials gives a detailed explanation of some of the steps involved in constructing GAA transistors. While it is a bit technical, it should give a good idea of why more tools and more advanced tools are needed as we progress to more advanced transistor architectures:
“Hundreds of process steps are involved in making gate-all-around transistors. Compared to previous generation FinFETs, gate all-around transistors can increase logic cell area density by as much as 30% and reduce power consumption by as much as 25%. Let's take a closer look at five of the most important steps.
Number one, creating nanosheets. The stacked nanosheets are formed by using epitaxy to deposit alternating layers of silicon and silicon-germanium, each only about 35 atoms thick. First Applied’s Centura Prime Epi system pre- cleans the wafer to remove contaminants that can hinder epitaxial growth. Then the system uniformly deposits the silicon and silicon-germanium layers with uniformity of at least 99%. Once the nanosheets are completed, shallow trenches are etched to isolate the individual nanosheets. Then, multiple patterning, etch and deposition steps are used to create dummy gates that will later be removed and replaced with actual gates.
The second major challenge is creating perfectly formed cavities on the ends of each silicon-germanium channel where a spacer is deposited to isolate the transistor's gate from its source and drain. Applied’s Producer Selectra Etch system pre-cleans the ends of the silicon-germanium channels, then laterally removes material. The system creates perfectly uniform box-shaped cavities that optimize transistor performance. Next, Applied’s PROvision eBeam Metrology system is used to measure the recess uniformity with nanometer resolution. Once the silicon-germanium channels are recessed, insulating dielectric material is deposited over the transistors and then carefully selectively etched away, leaving dielectric spacer material only in the cavity regions.
The third challenge is removing portions of the ends of the silicon nanosheets to create spaces where epitaxy is used to deposit high doping material that will tune the performance of the transistor source and drain. Applied’s Producer Selectra Edge system pre-cleans the ends of the silicon and then removes the material to laterally shape the channels. Next, the Centura Prime system pre- cleans the source and drain cavities and then uses selective epitaxy to precisely deposit doped silicon to form the source and drain. Selective epitaxy is a slow and well-controlled process to ensure material is uniformly deposited into the cavities from the bottom up. Once the source and drain engineering is completed, the spaces between the nanosheet-based devices are filled with a dielectric that isolates the transistors from one another. The transistors are then planarized down to the dummy gate structures which are etched to create gate cavities that expose the channels.
The fourth challenge is completely removing the sacrificial silicon-germanium channels. Applied’s Producer Selectra system is used to remove material, resulting in uniform silicon nanosheets. Applied’s Prime Vision eBeam inspection system is used to ensure no silicon-germanium residue is left on the nanosheets. If the process recipe leaves any residue, the eBeam review system is used to analyze the defectivity and tune the recipe until it's perfect.
The fifth critical engineering challenge is creating the metal gates that help the transistor switch from off to on at the precise threshold voltages. Engineering the threshold voltages involves varying the composition and thickness of the layers of metal deposited around each of the silicon nanosheets. In gate-all-around, the space between silicon channels is typically below 10 nanometres. In this tiny space, Applied developed an integrated material solution based on the the Endura platform to diffuse a dipole into the dielectric gate layer that surrounds the nanosheets. This step tunes the threshold voltage without adding any volume. Next, multiple layers of metal are atomically deposited in the narrow space. Once the transistor metal gates are tuned, several etch steps are used to partition the larger gate structure.”
In between these steps, wafers travel between the various areas of a fab to undergo treatment. You can observe in the schematic below how there are three key areas in a fab - photolithography (green), deposition (blue) and etch (red):
The typical workflow is deposition, photolithography and then etch, with a few other steps in between such as coating and ion implantation. These steps are subsequently repeated hundreds of times.
Both ASML and Applied have been working on creating a holistic feedback loop, with data from their eBeam inspection systems being streamed into their key manufacturing tools to recalibrate them. ASML acquired Taiwanese Hermes Microvision almost a decade ago now to achieve this purpose.
These algorithms are now also running on Nvidia GPUs, so in a way, currently GPUs are building even more advanced GPUs in TSMC’s fabs as we speak.
The story of ever more advanced transistor architures is far from over. Belgium-based Imec is at the forefront of this, and we have a roadmap well into the next decade. After nanosheets, we get CFETs, and possibly after that 2DFETs:
A CFET is basically two GAA cells stacked on top of each other:
This is Lam’s CEO at Bernstein explaining how etch and deposition tools are a great play on the introduction of more complex 3D transistors:
“Lam is a company that is focused on etch and deposition. And etch and deposition are two of the fastest-growing segments within wafer fabrication equipment, primarily because these are the types of equipment that are needed to build all of these complex 3-dimensional structures. These are the types of equipment that are required to deposit all of these new materials and etch those materials. So they're really fundamental to several of the really critical technology inflections accruing about. We look at foundry logic and Lam is a big player in the gate-all-around inflection.
So we focused on those areas, introducing new products including ALD (atomic layer deposition) and selective etch. You look at things like backside power delivery, another foundry logic inflection, you're now having very thick interconnect layers on the backside of the wafer. This is what we're great at, electroplating and thick film deposition with high productivity. You look at other inflections in DRAM, for instance HBM, the building of 3-dimensional memory structures. We see plenty of opportunity to grow our business.
We talked about four $1 billion opportunities ahead of us. And from when we put out those numbers, they're sort of accelerating a little faster. Gate-all-around already this year, we're going to have $1 billion in shipments, and also our advanced packaging business is $1 billion of shipments this year. Backside power, we said that would be about a $1 billion opportunity for us, and the last inflection is dry EUV resist, also a $1 billion-plus opportunity.
We only address about mid-30s percent of WFE with our served market today, that compares to some of our peers who are well over 50%. And so that means we can be very laser-focused on where we think the greatest opportunity is to apply our skills and expertise.”
Lam’s CFO gave some further details at the BoA conference:
“When I look at the evolution of architectures, in most of the industry, things are going in the third dimension. That's largely what Lam Research does for the industry. When things go 3D, like NAND did a decade ago, our addressable market doubled. And you see that beginning to happen today in areas like gate-all-around. Our addressable market is going to grow meaningfully and the metric we put out is, it looks like $1 billion for every 100,000 wafer starts that we can address around things like selective etch and ALD. And frankly, when you look at some of these accelerator dies, the GPU is at the reticle limit. It can't get any bigger. And so how does the industry evolve in a situation like that? Advanced packaging. You start to hear the industry talk about chiplets and heterogeneous integration and to create those structures, you need equipment to do the drill and fill, and we are uniquely positioned in TSV (through-silicon-via) as an example.”
An overview of transistor scaling and going 3D:
An example of ‘drill-and-fill’ illustrated below, through-silicon-vias (TSVs) are used to connect dies, both 2.5D chiplets and vertically stacked ones such as in HBM.
So the above TSVs are used to make a connected system of dies like this:
This is Applied’s CEO at Bernstein on the opportunity they’re seeing:
“The whole focus around power consumption and energy-efficient computing, that's really the focus for us. Big inflections like gate-all-around, a 30% improvement in power consumption, then you have backside power, where you move the power lines to the back of the wafer, a 25% improvement in power consumption. You have packaging technologies, that's a $1.7 billion business for us today and we said that business can more than double going forward. Within Applied, we have the broadest connected portfolio in the industry and when you think about those big inflections, we can capture over 50% of the incremental spending for gate-all-around, and in backside power, 50% of that spending.”
For premium subscribers, we’ll take an in-depth look at:
Applied Materials’ platform strategy
The new tech developed by Lam Research and Tokyo Electron
An analysis of Applied Materials, Lam Research and Tokyo Electron
Thoughts on the current Chinese semicap boom
A comparison of the key financial metrics for the various semicap names
Concluding thoughts on the space and which names are likely best for long term investors
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