Cadence & Synopsys, next winners from AI
Cadence & Synopsys, next winners from AI
What's next in EDA
An introduction to the EDA space
Both Cadence and Synopsys are active in electronic design automation (EDA) software, which is used to design and analyze integrated circuits (ICs) and printed circuit boards (PCBs). This should be an attractive industry for long term investors as the top three vendors — Synopsys, Cadence and Siemens — control around 75% of the market. There is not any real risk of new competitors entering at the moment, even in the Chinese market — where the drive will be substantial to transition to homegrown technologies — the leading player only has a 1% market share currently.
The great thing about software businesses is that revenues are largely recurring via subscription models, so investors already know beforehand how much cash will be coming in as opposed to hardware businesses such as semiconductors which can be notoriously cyclical. On top of that, pricing power is strong as clients don’t tend to switch software providers. You would have to retrain your engineering force on new software which will take months. As the costs of semi design are already getting out of control, e.g. with the design of a state of the art chip costing nearly $1 billion, naturally the semi designer sticks with the best software.
This has resulted in attractive revenue growth for both Cadence and Synopsys:
Growth picked as design costs at the leading nodes increased, with more transistor counts requiring a larger team of design engineers as well as more software to run for example an increasing amount of simulations to verify the chip design.
Arm provides the following estimates for the rise in semi design costs on the leading nodes:
Percentage-wise the biggest jumps occurred at 7 and 5nm with the introduction of EUV (initially quadruple DUV patterning as EUV wasn’t ready). According to the data, these increases would moderate on 3 and 2nm:
If this analysis from IBS is correct, large tailwinds which the EDA companies have been enjoying would start moderating, which could give a drop in top line growth rates. However, long term growth rates should remain attractive nevertheless, as EDA revenues are correlated with semi R&D spend, which in turn is correlated to how many transistors are going into a single chip. On the latter, we have a clear roadmap for the number of transistors within a single die to keep increasing for more than a decade, with both the move to both GAA and CFET type transistors (illustrated by Imec below).
Another trend which will benefit the EDA players is custom silicon, with large companies such as Apple, Amazon, Google, Microsoft and Tesla increasingly in favor of designing their own chips. This means their in-house design teams will need more EDA software as well.
Currently hyperscalers are working with specialist semi designers such as Broadcom and Marvell to develop these specialized custom chips, however, Cadence’s CEO view is that long term they’ll likely take this fully in-house: “The cloud companies, they’re all working very closely with the 2 or 3 main ASIC companies because what happens is when the big system companies do silicon design, they don’t do all of it in-house immediately. They will do the front-end in-house and then do the back-end with an ASIC company. And then later on, they can move the whole thing in-house.”
An additional trend in favor of the EDA industry is that semiconductors are seeing increasing applications in a wider variety of end markets, such as automotive, industrials, and AI datacenters. Chips need to be tailored for these specific end markets, which again bodes well for EDA demand.
And as already mentioned, pricing power in the industry is strong, which means that we should see regular price increases above the rates of inflation.
The below chart nicely illustrates where EDA sits in the semi value chain. Taking out the IP part from the number below, the overall EDA market is around 1.5% of the size of the semiconductor market. If around 15% of the semiconductor market is spend on R&D, this means EDA software is around 10% of the R&D budget. A bit further up we’ll go through why this number is likely to increase.
This broader EDA market can be further segmented by the type of semiconductor and the type of workload, where there usually is one software tool which is dominating with a market share of 40% of above. Historically, Cadence was the strong player in analog and Synopsys in digital, but both players now provide a broad portfolio of tools. As the design flow of a chip takes up a series of tools, typically both Synopsys and Cadence have all the top semi designers as their customers, with their customers typically selecting the best of breed tool for each particular task. Siemens acquired the pioneering Mentor Graphics business in 2017, which has now been rebranded under the Siemens brand.
Most of semi design happens in a textual programming language while letting the software tools optimize the chip’s physical design based on these instructions. It is therefore clearly mathematics-heavy software. Connecting trillions of transistors by hand is obviously not feasible, no matter how large your engineering team is.
A simple example of how you can code an inverter in VHDL, a hardware description language used in EDA, is shown below:
During and after the design, regular rounds of simulations will be ran to find bugs. When the chip design is nearing completion, the chip can also be emulated on physical hardware so that accompanying software can be tested on top of it. This way, you can also further develop your hard- and software in parallel while testing both on each other. Large companies such as Nvidia can also provide the emulation hardware of their latest GPUs to large clients, so that those can already start testing the GPUs while building additional software on top. Similarly, the automotive sector is increasingly relying on emulation to start testing their self-driving software on chips still in development. At the end of the design process, when the chip designer is confident that all is working well, he can send the blueprints to TSMC for a tapeout, which can be pricey. If all goes well again, the actual first silicon can then be fabricated and tested, after which the designer can start handing out samples of the product to clients.
The big three players have now been dominating the EDA industry for a few decades. Over the years, both Synopsys and Cadence have been cobbling up smaller niche players in the industry to build up a complete portfolio of software tools, aimed at automating the entire chip design workflow.
AI as the next driver
So, IBS is saying that design cost increases would start moderating from here, which would be a negative for EDA. However, what got me enthused again on the space is that with the use of AI, EDA can become a larger part of semi R&D spend, also while addressing the current shortage in semi engineers. Cadence’s CEO detailed this at the Bernstein conference:
“So EDA for 30 years has been very complicated software but one thing we never did was workflow automation. So EDS software has always been what I would call single run, you give it an input and it gives the output. Say, I want this kind of CPU, it will run for 1 or 2 days typically and do all kinds of optimization and geometric processing. If you go to all big customers of ours, they typically will run Innovus, which is one of the flagship implementation tools. They’ll change something, and they will run it again. Either the process or the design spec changes, or they are exploring the design space for the best power or performance. So what we can do with reinforcement learning, and we have several tools, but one of the tools in implementation is called Cerebrus. It automates that running of searching the design space. So it’s huge value because you’re replacing something that was manual before. What used to take 2 days in one run, if you run it on ten machines in parallel with reinforcement learning, it takes about one week, but 200 runs. So you are replacing like months of work. But what is even more powerful is that the results can be better than achieved by humans, because it’s very difficult to optimize on 17 dimensions. In a lot of cases, we have 5 to 10% better PPA (power, performance and area) than the old way of doing it. So there is a lot of opportunity to capture a bigger percentage of R&D spend. We now have 10 out of the top 20 customers and five big hyperscalers using it. Today, we have 100 billion transistors, by end of the decade, it will be 1 trillion transistors. So the size is going up by 10x but the amount of work is probably going up by 30 to 40x. There is no way to hire 30 to 40 times more engineers. There are not even that many graduating. So what I expect will happen is that the customers will still hire more engineers, maybe like 2 to 3 times more than now but for the rest of the productivity gap, there is an opportunity for a bigger portion of R&D to go to automation.”
Having the amount of work required to design a leading edge chip go up by 30 to 40 times and the amount of work carried out by the EDA software go up 10x is obviously interesting. Especially as the business model is shifting towards billing based on workloads. Cadence’s CEO explaining this:
“EDA is almost all subscriptions, on the emulation hardware, there is some upfront component. Now, some customers will lease the hardware, so it’s subscription, but some big customers will buy it. Overall, our revenue is about 85 to 90% subscription which is great these days. And with a 99% renewal rate or more. Unless the company goes out of business, they will typically renew. And then we have different business models, some products are tied to the number of engineers, but more and more it’s tied to the amount of work that is happening.”
Synopsys’ CFO added some details how the semi designers are using AI tools and how the company is thinking about monetizing these, from the Bank of America conference: “And our first tool is DSO.ai, that’s design space optimization. So the way we monetize it, is you buy our underlying subscription and then you buy the DSO.ai tool per project. And what we’re finding with customers is as they’re running multiple iterations to optimize the design, they actually use more of the underlying tools because they only have a certain amount of time. And so if they have more tools from us, they can run more iterations. What we also announced at the end of March is that we’re launching TSO.ai (for testing) and VSO.ai (for verification). So we’re building AI tools out across the entire design flow. We’re really focused on making sure that we’re driving broad adoption so we can have successful use cases and we’ll experiment over time with additional monetization. It’s one of the reasons that we’re growing faster than the underlying R&D spend.”
Nvidia recently announced that they will be shifting from a two year to a one year cadence in the release of new datacenter GPUs. Clever usage of new AI tools is probably playing a role here, with both Cadence and Synopsys executives commenting that AI tools are being used to accelerate the optimization of the design space. The good news for EDA players is that this should also allow Nvidia’s competitors to move to a faster cadence compared to previously.
Overall, my impression is that these novel AI tools: a) are seeing adoption, b) have strong benefits, especially in speeding up R&D as well as in the final product’s PPA, and c) pricing can be done based on workloads which allows for these benefits to be partly monetized by the EDA industry.
For premium subscribers, we’ll further dive into:
How AI is being implemented into EDA tools
How AI will impact the EDA industry, including whether this can result in further consolidation
An analysis of both Cadence’s and Synopsys’ businesses
The introduction of Chinese export sanctions by Washington
Chinese EDA competition
A financial analysis and thoughts on valuation for both Cadence and Synopsys